Pipelined analog-to-digit converter comparator offset foreground calibration circuit and method
A technology of analog-to-digital converter and calibration circuit, which is applied in the directions of analog/digital conversion calibration/test, analog/digital conversion, code conversion, etc., which can solve the problem that the dynamic offset error of the comparator cannot be solved, and achieve strong technical portability , The effect of occupying a small chip area
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[0057] The circuit and method provided by the invention are calibrated for the key module comparator in the pipeline analog-to-digital converter, which can greatly reduce the offset error of the comparator without introducing excessive power consumption. This technology has been successfully used in the first and second pipeline stages of a certain 16-bit pipeline analog-to-digital converter. The maximum absolute value of the offset voltage of the original comparator is about ±60mV. After using this calibration technique to set the number of cycle comparisons to 65536, the maximum absolute value of the offset voltage drops to about ±1mV. When this calibration method is not used, the integral error INL of the converter can reach a maximum value of about 20LSB, such as Figure 5 shown. After using this calibration method, the maximum value is only about 2LSB, such as Figure 6 shown. Compared with other inventions, the invention does not introduce static power consumption dur...
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