DDR (double data rate) wiring wire length detection method and system

Abstract

The invention discloses a DDR (double data rate) wiring wire length detection method which includes the steps: acquiring network types selected by users and dividing the network types selected by theusers into corresponding signal sets; reading the length of each network signal wire in each signal set; calculating intra-set wire length difference values and / or inter-set wire length difference values of the signal sets according to the length of each network signal wire in each signal set. Besides, the invention further discloses a DDR wiring wire length detection system which comprises an acquisition module, a grouping module, a reading module and a processing module, wherein the acquisition module is used for acquiring the network types selected by the users, the grouping module is usedfor dividing the network types selected by the users and acquired by the acquisition module into the corresponding signal sets, the reading module is used for reading the length of each network signalwire in each signal set, and the processing module is used for calculating the intra-set wire length difference values and / or inter-set wire length difference values of the signal sets according to the length of each network signal wire in each signal set. Testing operation steps are simplified, redundant workload is reduced, and working efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of DDR wiring, in particular to a line length detection method and system for DDR wiring. Background technique [0002] One of the wiring requirements of the DDR PCB Layout is to meet the equal-length requirements of the DDR signal wiring, because the length of the signal line will affect the timing and signal quality of the DDR. The requirements for long Layuot wiring such as DDR often appear in CPU specifications. For example (with Figure 1a and 1b It is the datasheet of two CPUs), which generally includes the requirements of equal length within the group and equal length between groups. These data are difficult to obtain directly and often require more complex measurements and calculations. from Figure 1a and Figure 1b It can be seen that the equal length control of DDR wiring basically controls the following aspects: [0003] (1) The CK signal differential pair is equal in length, which must meet...

AI Technical Summary

Problems solved by technology

[0003] (1) The CK signal differential pair is equal in length, which must meet the error range

[0004] (2) The DQS signal differential pair is equal in length, which must meet the error range

[0010] (2) Complicated calculation

There are many equal-length requirements, and the calculation is more complicated

[0011] (3) The final data is not intuitive

Not having a conclusive record form

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