CVSD (Continuously Variable Slope Delta Modulation) digital pressure amplification modulation principle analysis experiment method and system
A technology of incremental modulation and experimental method, which is applied in the field of communication, can solve problems such as inability to intuitively reflect the encoding process, inability to accurately analyze the comparison results of the quantization order signal and the input analog signal, and the help effect is not obvious.
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Embodiment 1
[0030] This embodiment is to provide a CVSD digital pressure amplification modulation principle analysis experimental method based on the STM32 microprocessor. The experimental system uses the STM32 software synchronization algorithm to ensure that the input analog signal, quantization level signal, and binary coded signal are in one syllable. Absolute synchronization within the period. At the same time, by controlling the STM32, the analog signal waveform, the syllable period on the time axis, the quantization step signal, and the encoding signal can be observed on the same LCD screen at the same time. The frequency and amplitude of the input analog signal can be accurately observed The change of the coded output data, the level of quantization step, the number of consecutive code bits caused by the change, and the comparative relationship between the amplitude of the quantization step signal and the input analog signal. The STM32 microprocessor is used to simultaneously displa...
Embodiment 2
[0052] A CVSD digital pressure amplification volume modulation principle analysis experimental system that implements most of the methods in Example 1, such as image 3 As shown, the STM32 microprocessor chip 5 is included, and the STM32 microprocessor chip contains figure 2 The shown subtractor, judge, pulse amplitude modulation integrator, continuous code detection and processing modules for sampling audio analog signals and continuous code detection sampling; a frequency range of 300HZ-3400HZ is provided around the microprocessor chip Bandwidth limiting circuit 6 and digital liquid crystal display 7; the input end of the bandwidth limiting circuit is connected to the audio analog signal acquisition circuit 8, the output end of the bandwidth limiting circuit is connected to the A / D conversion input interface of the microprocessor chip, and the liquid crystal display passes The interface circuit 9 is connected to the data output line of the microprocessor chip, and a band-limit...
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