An integrated circuit structure and its manufacturing method, and a semiconductor device

Abstract

The invention discloses a manufacturing method of an integrated circuit structure. The manufacturing method comprises the steps of: providing a first wafer on which a first circuit structure and a first top-layer passivation layer thereon are formed; providing a second wafer, wherein alignment marks are formed on the first surface of the second wafer; forming second doped regions of a second circuit structure on the second wafer; making the first surface of the second wafer face toward the first top-layer passivation layer to perform bonding of the first wafer and the second wafer; thinning the second wafer to the second doped regions; forming second gates and a second interconnection structure of the second circuit structure on the second wafer, and forming inter-wafer interconnecting lines between one layer of the second interconnection structure and one layer of a first interconnection structure of the first circuit structure; and covering a second top-layer passivation layer. According to the manufacturing method, the distance between the inter-wafer interconnection lines is equal to the distance between lead wires in a chip, the inter-chip conduction distance is smaller, the inter-chip conduction can be achieved without large-sized through holes, the process is easy to implement and the integration degree is high.

Description

technical field [0001] The invention belongs to the field of semiconductor device manufacturing, and in particular relates to an integrated circuit structure, a manufacturing method thereof, and a semiconductor device. Background technique [0002] With the continuous development of integrated circuit technology, the size continues to shrink according to the law of "Moore's Law" to continuously improve the integration level, but the traditional device size will reach its own physical limit when it is reduced to a certain extent, and the reduction of integrated circuits in the plane has become increasingly more difficult. [0003] At present, the three-dimensional stacking technology of integrated circuits that expands towards the Z axis is a development direction. It is formed by combining multiple wafers. Via) are connected to each other in the Z direction. [0004] However, as the requirements for integrated circuit functions are getting higher and higher, the structure ...

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Problems solved by technology

[0004] However, as the requirements for integrated circuit functions are getting higher and higher, the structure of devices is becoming more and more complex, and the size is getting smaller and smaller. The realization of deeper through-silicon vias requires larger openings. The realization of through-silicon vias more and more difficult

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