A kind of semiconductor device and its preparation method, electronic device

Abstract

The invention relates to a semiconductor device, a preparation method thereof, and an electronic device. The preparation method comprises: providing a semiconductor substrate including a central region and an edge region, wherein a plurality of floating gate structures are formed in the semiconductor substrate and shallow trench isolation structures are formed between the adjacent floating gate structures and downwardly extend to the semiconductor substrate; removing a part of oxide in the shallow trench isolation structures by using etching back in order to form a groove and expose a part of the sidewalls of the floating gate structures; depositing a covering layer in order to fill the groove and cover the floating gate structures; and removing a part of the covering layer by using wet etching in order to expose a part of the sidewalls of the floating gate structures again. The method further deposits the covering layer after a COPEN processing step, then removes the covering layer by using wet etching, and leaves a part of the covering layer at the edge region in order to compensate the thickness of the oxide in the edge area, thereby improving device performance and yield.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and in particular, the invention relates to a semiconductor device, a preparation method thereof, and an electronic device. Background technique [0002] With the increasing demand for high-capacity semiconductor storage devices, the integration density of these semiconductor storage devices has received more attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art, such as through Reducing the size of the memory cell and / or changing the structure of the unit to form more memory cells on a single wafer, as for the method of increasing the integration density by changing the cell structure, attempts have been made by changing the planar layout of the active region or changing Cell layout to reduce cell area. [0003] NAND flash memory is a better storage solution than hard disk drives. Since NAND ...

AI Technical Summary

Problems solved by technology

[0005] In the COPEN process, the thickness of the oxide removed in the central area and the edge area of ​​the wafer is inconsistent, causing the height of the residual oxide to be uneven, thereby causing the unevenness of the threshold voltage of the semiconductor device, making the device's Performance and yield degradation

Images