A clock source for serializer/deserializer based on clock manager and fpga

Abstract

The invention discloses a serializer / deserializer clock source based on clock managers and an FPGA. According to the work principle of the serializer / deserializer clock source, main backup clock signals transmitted by a backboard are received by the FPGA, due to the features of the adopted clock managers, after being powered on, the FPGA can transmit the main backup clock signals to the first clock manager and the second clock manager, and after the first clock manager and the second clock manager are configured successfully, clock signals with the same phase frequency or the different phase frequencies can be output. The FPGA outputs eight paths of clock signals to a SerDes, the first clock manager and the second clock manager output eight paths of clock signals to the SerDes, a main backup relation is formed by the clock signals output by the FPGA and the clock signals output by the two clock managers, the final clock source can be selected in actual work according to a debugging result, the design flexibility is facilitated, and the design reliability is improved.

Description

technical field [0001] The invention relates to a serial / deserializer clock source based on a clock manager and FPGA, which is applied to a remote sensing camera video processor using the serial / deserializer. Background technique [0002] With the sharp increase in the amount of data acquired by some remote sensing cameras, the corresponding data transmission rate has also continued to increase. Using SerDes devices (serial / deserializers) to achieve high-speed data transmission has become the first choice, but SerDes devices have higher clock speeds. However, considering the problem of homologous clocks in many cameras, it is inevitable that there will be long-term clock transmission. At present, FPGAs are widely used to provide clock sources for SerDes devices, but the clocks transmitted by FPGAs from the backplane may be unstable. Afterwards, affected by various factors such as PCB layout and electromagnetic interference, the quality of the clock may decline, and then tran...

AI Technical Summary

Problems solved by technology

[0002] With the sharp increase in the amount of data acquired by some remote sensing cameras, the corresponding data transmission rate has also continued to increase. Using SerDes devices (serial / deserializers) to achieve high-speed data transmission has become the first choice, but SerDes devices have higher clock speeds. However, considering the problem of homologous clocks in many cameras, it is inevitable that there will be long-term clock transmission. At present, FPGAs are widely used to provide clock sources for SerDes devices, but the clocks transmitted by FPGAs from the backplane may be unstable. , and then affected by various factors such as PCB layout and electromagnetic interference, the clock quality may decline, and then transmitted to the SerDes device through the FPGA, there may be a high bit error rate, which will affect the final image quality

Images