ddr2 SDRAM controller

Abstract

The invention relates to a double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) controller. Due to the fact that the DDR2SDRAM controller follows a DDR2SDRAM interface protocol, data transmission between the DDR2SDRAM controller and an outside DDR2SDRAM is achieved. The DDR2SDRAM controller comprises a DDR2SDRAM interface, a system data bus interface, an order arbiter and a command queuing and reordering module, wherein the DDR2SDRAM interface achieves various signals a DDR2SDRAM interface protocol definition; the system data bus interface achieves an interface function of the sides of system data buses and can be copied to meet requirements of the connection of a plurality of data buses; the order arbiter aims at requests of the plurality of data buses and enables only one route of data bus to visit the outside DDR2SDRAM within the same time; the command queuing and reordering module receives a reading / writing request command which is output by the order arbiter, the reading / writing request command is reordered according to relevancy of an address, and thereby the use ratio of the DDR2SDRAM interface is improved.

Description

technical field [0001] The invention relates to a DDR2 SDRAM controller. Background technique [0002] At present, DDR2SDRAM is widely used, and many application systems will use DDR2SDRAM as memory. Compared with DDRSDRAM, DDR2SDRAM has the characteristics of low power consumption and high available bandwidth, so it is especially suitable for video codec, image processing, etc. that require large data throughput. application occasions. [0003] First of all, the data bandwidth that DDR2SDRAM can provide is determined by the following formula 1: [0004] Data bandwidth = data line bit width * 2 * clock frequency * utilization rate (Formula 1) [0005] Due to the natural properties of DDR2SDRAM, there are many additional operations in the process of transmitting data, such as activating the corresponding bank according to the address, and timing refresh (REF) operations, etc., so DDR2SDRAM does not transmit data every clock cycle , How to maximize the theoretical bandwidth...

AI Technical Summary

Problems solved by technology

If the data bandwidth required by the entire system is large, then the DDR2SDRAM controller must work at a higher clock frequency, so there is a clock frequency requirement for the data bus (DataBus) that needs to access the external DDR2SDRAM, at least the data bus output The data bus clock must be consistent with the DDR2 SDRAM controller. Although the fully synchronous design is relatively simple, it sacrifices the convenience of use

For example, if a DDR2-800 SDRAM is connected externally, then the DDR2 SDRAM controller needs to work at a clock frequency of 400MHz at most to obtain the maximum data bandwidth, and some data buses in the system do not require such a high operating frequency. But in order to access external DDR2SDRAM, these data buses may be modified to meet the clock frequency requirements

[0010] (2) Lower bandwidth utilization

Reduced bandwidth utilization in some cases due to lack of reordering of read / write request commands

Images