Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller

Abstract

The invention is applied to the technical field of electronics, which provides a method and a system for verifying a timing sequence calibration function of a dynamic random access memory (DRAM) controller. The method comprises steps of performing static delay according to preset static delay value which is random value or traverse value in designated range; generating a test case event describing operations executed by a data transmission bus connected with the DRAM controller; generating a control event according to the test case event; monitoring and obtaining a monitoring event which includes an order part and a data part; and obtaining accurate timing sequence calibration of the DRAM controller when the order part and the data part in the monitoring event are respectively identical with an order part and a data part in the control event. By means of the preset static delay value generated in random or traversal mode in the designated range, the timing sequence calibration function of the DRAM controller is verified, thereby achieving the purpose of verifying the timing sequence calibration function as comprehensive as possible and obtaining complete verification.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a verification method and system for a timing verification function of a DRAM controller. Background technique [0002] With the development of processor technology, the front-side bus has higher and higher requirements for memory bandwidth, so the frequency requirements for memory are also higher and higher. While the frequency of memory is increasing, in order to obtain stable and correct data, it is necessary to read When writing data, the timing of related signals is strictly controlled, because when the bus frequency is high, the static timing is uncertain, which may lead to data reading and writing errors. When writing to the memory, the timing of related signals is changed by dynamic The random access memory (Dynamic random access memory, DRAM) controller does not need to perform a static delay verification operation on related signals, so the static delay ...

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Problems solved by technology

[0004] The purpose of the embodiments of the present invention is to provide a verification method for the timing verification function of the DRAM controller, which aims to solve the problem that the motherboards in the actual application of the prior art are different, and it is impossible to test all possible motherboards completely, so the actual The problem of low coverage in the case of verification

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