Clock generating and smoothing device

Abstract

The invention discloses a clock generating and smoothing device which comprises an FIFO (First In First Out), a step length regulation module and a counter, wherein high-speed SDH (Synchronous Digital Hierarchy) data is taken as input data of the FIFO, an SDH clock is taken as a write clock of the FIFO, a high-speed reference clock is taken as a read clock and is used for reading data in the FIFO, the step length regulation module and the counter, and the data read from the FIFO is low-speed PHD (Pulse Height Detection) data. The FIFO uses deep data and sends the deep data to the step length regulation module, the step length regulation module outputs an accumulated step value to the counter subjected to judgment, the counter carries out accumulation according to the step value to obtain a counting value, and an output signal is reversed after the counting value reaches an upper limit to finally generate a smooth PHD clock. A PHD clock signal generated by applying the clock generating and smoothing device is smooth and can efficiently avoid error codes caused by misjudgment of a chip at downstream.

Description

technical field [0001] The invention relates to a device in the technical field of communication, in particular to a clock generating and smoothing device. Background technique [0002] During SDH signal transmission, low-speed PDH signals need to be multiplexed and demultiplexed. The rate of the tributary signal including PDH demultiplexed from the SDH signal still maintains the high-speed SDH signal rate, and the rate of the PDH signal needs to be reduced to the rate of the normal PDH signal in order to send it to the PDH frame processing chip for each PDH signal. kind of operation. Currently, since the rate of the PDH signal and the rate of the SDH signal are not in an integer multiple, the clock of the PDH signal generated by demultiplexing is irregular, which may easily cause misjudgment by downstream chips and generate bit errors. Contents of the invention [0003] The present invention aims to provide a clock generation and smoothing device capable of generating a...

AI Technical Summary

Problems solved by technology

At present, since the PDH signal rate and the SDH signal rate are not integer multiples, the PDH signal clock generated by demultiplexing is irregular, which may easily cause misjudgment by downstream chips and cause bit errors.

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