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Method for anti-interference encryption in bus expansion

A bus and function technology, applied in the field of anti-interference encryption of bus expansion, can solve the problems of weak anti-interference ability, high parallel bus speed, single-board design, etc., achieve high-reliability design, improve reliability, and improve anti-interference. Effect

Active Publication Date: 2010-11-03
ZHUHAI XJ ELECTRIC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the high speed of the parallel bus and weak anti-interference ability, its application is often limited to single-board design, and there are many technical difficulties in the application of multiple plug-ins in the whole machine.

Method used

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  • Method for anti-interference encryption in bus expansion
  • Method for anti-interference encryption in bus expansion
  • Method for anti-interference encryption in bus expansion

Examples

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Embodiment 1

[0024] The present invention will be described in detail below. Firstly, the data bus is divided into regions, and the functions of each partition are specifically defined. In this case, a 16-bit bus is taken as an example for illustration. The 16-bit parallel bus data is divided into four areas: control enable area, instruction effective area, control area and control check area (also called "bus bit-wise partition encryption method"). The 16-bit data bus partition is shown in the following table:

[0025]

[0026] Among them, the control enable area: the code Bit15~Bit12 can be set to 0101, which corresponds to the general enable command of the function plug-in hardware controlled, and the code should correspond to the function and number of the function plug-in.

[0027] Instruction effective area: Bit11~Bit8 can be fixedly coded as 0101, which is used as the central CPU instruction enable password, indicating that the control instruction is effectively given by the CPU....

Embodiment 2

[0039] On the basis of the bus space encryption in the first embodiment above, a time-sharing dual instruction verification mode is adopted to realize bus time encryption. Such as figure 2 As shown, the principle is that before the central CPU issues the bus control command, it first issues the valid bus enable command. After the functional plug-in correctly receives the valid bus enable command, the functional plug-in starts to receive the bus control command and continues to receive the waiting time. 0.1ms (this time can be set according to the bus speed), if the function plug-in receives the control command conforming to the bus space encryption within this time, it will control out, if it exceeds 0.1ms, the function plug-in will refuse to receive the bus control command, that is, the central The CPU considers this control failure. The time encryption instruction format may be the same as the space encryption format. The specific timing diagram is as follows, Δt is the r...

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Abstract

The invention discloses a method for anti-interference encryption in bus expansion. The method realizes the high accuracy and high anti-interference performance in the real-time transmission of bus data. In the method, the bus data are divided into four areas, namely a control enabling area, an instruction coverage area, a control area and a control verification area, in a central processing unit (CPU), and the data are encrypted spatially, so the anti-interference performance is improved, a highly reliable design scheme is provided for system design at a high speed, and a new parallel bus application mode is created. The method for the anti-interference encryption in bus expansion can be applied in the fields of power systems, industrial control, power electronics, aerospace and the like.

Description

technical field [0001] The invention relates to a bus external expansion anti-interference encryption method. Background technique [0002] When systems such as CPU or MCU have a parallel bus, the expansion slot of the parallel bus is usually used to realize the expansion application of the function plug-in. In the power terminal products, for any CPU system design, the application of the data / address parallel bus is already very extensive. , In short-distance transmission within the board, this application method not only has fast transmission speed and high efficiency, but also is less prone to errors. However, due to the high speed and weak anti-interference ability of the parallel bus, its application is often limited to single-board design, and there are many technical difficulties in the application of multiple plug-ins in the whole machine. Contents of the invention [0003] The technical problem to be solved by the present invention is to overcome the deficiencies...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38G06F13/42
Inventor 刘海龙魏东东郭上华
Owner ZHUHAI XJ ELECTRIC
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