Digital clock recovery PLL
a phase locked loop and clock technology, applied in the field of digital clock recovery, can solve the problems of source data being subject to periods of data dropout, unable to recover, acquisition of clock signals, etc., and achieve the effect of reducing analysis overhead
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[0026]Referring to FIG. 1, a block diagram of a circuit 100 is shown in accordance with a preferred embodiment of the present invention. The circuit 100 may be implemented as a Digital Clock Recovery Phase Locked Loop (DCRPLL) circuit. The DCRPLL 100 may be a replacement for an Analog Clock Recovery Phase Locked Loop circuit (e.g., a very complex analog circuit used to extract clock and data information from a read channel data stream). The present invention may use digital logic to achieve the same functionality as provided by analog circuits. Therefore, the present invention may be implemented with modern technology, which expects reproducible, dependable performance when many different functions are integrated onto a single silicon integrated circuit.
[0027]The circuit 100 may have an input 102 that may receive a signal (e.g., DIN) and one or more of (i) a set of outputs 104 and 106 that may present serial data signals (e.g., DOUT and OCP), (ii) a set of outputs 108 and 110 that m...
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