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Structure and self-locating method of making capped chips
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a technology of capped chips and structures, applied in the field of microelectronic packaging, can solve the problems of requiring a relatively complex series of steps for forming terminals on caps, requiring a relatively complex series of steps, and providing terminals for mems devices
Inactive Publication Date: 2005-04-21
TESSERA INC
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This increases the area of the active wafer required to form each unit, requires additional operations and results in an assembly considerably larger than the unit itself.
However, formation of terminals on the caps and vias for connecting the terminals to the contacts on the active wafer requires a relatively complex series-of steps.
Similar problems occur in providing terminals for MEMS devices.
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[0153]FIGS. 1-3D illustrate a capped chip and stages in a method for fabricating a capped chip according to an embodiment of the invention. In particular, FIG. 3C is a sectional view illustrating a capped chip 200 and FIG. 3D is a plan view illustrating the interconnects and the seal provided on the surface of a chip included in the capped chip.
[0154] Particular types of devices, such as SAW devices and MEMs need to be sealed hermetically in order to function appropriately over the life of the device. For many silicon semiconductor devices, a package is considered to be hermitic if it has a leak rate of helium below 1×10−8 Pa m3 / sec. Other devices such as electro-optical devices do not require hermeticity, but nevertheless are best packaged under a protective lid, e.g., one that is optically transmissive, as a way of preventing particles from reaching a surface of the electro-optic device.
[0155] In a method of forming the capped chips, a plurality of caps 102, e.g., as contained i...
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Abstract
A method of making the lidded chip assembly are provided which includes the steps of: (a) aligning a lid member with a chip member including one or more chips so that electrically conductive elements projecting from a front surface of the chip-member extend into through-holes in the lid member and at least partially control location of the lid member relative to the chip member in one or more horizontal directions parallel to the front surface; and (b) forming interconnections extending through the lid member so that the interconnections include the conductive elements. A capped chip is provided in which the conductive interconnects extend from the chip through openings in a cap member, the openings being tapered to become smaller in a direction from the bottom or inner surface of the opening towards the top or outer surface.
Description
[0001] This application claims the benefit of the filing dates of U.S. Provisional Patent Application Nos. 60 / 506,500 filed Sep. 26, 2003, 60 / 515,615 filed Oct. 29, 2003, 60 / 532,341 filed Dec. 23, 2003, 60 / 568,041 filed May 4, 2004, 60 / 574,523 filed May 26, 2004, and is a continuation-in-part of U.S. patent application Ser. No. 10 / 928,839, filed Aug. 27, 2004 entitled PACKAGE HAVING INTEGRAL LENS AND WAFER SCALE FABRICATION METHOD THEREFOR, on which Catherine De Villeneuve, Giles Humpston, and David B. Tuckerman are named inventors, the disclosures of all such applications being hereby incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] The present invention relates to microelectronic packaging. Microelectronic chips typically are thin, flat bodies with oppositely facing, generally planar front and rear surfaces and with edges extending between these surfaces. Chips generally have contacts on the front surface, which are electrically connected to the circuits within ...
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Patent Type & Authority Applications(United States)
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