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Systems and apparatuses for on-die memory power analytics and management

A memory and bare chip technology, used in static memory, CAD circuit design, electrical digital data processing, etc., can solve problems such as time-consuming

Inactive Publication Date: 2020-08-18
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Simulating the electrical response of a memory die by simulating every component in the memory die can be prohibitively time consuming

Method used

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  • Systems and apparatuses for on-die memory power analytics and management
  • Systems and apparatuses for on-die memory power analytics and management
  • Systems and apparatuses for on-die memory power analytics and management

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Embodiment Construction

[0018] A memory die may include a power distribution network (PDN) to distribute power across the memory die. For example, a memory die may include pads for receiving power from one or more power supplies or voltage sources, and power may be distributed across the die using a grid, such as resistors and conductive lines. In some cases, a memory die may experience a voltage drop between the pads of the memory die and various other components on the memory die during operation of the memory die, which may affect the performance of the components on the memory die. In some cases, it may be useful to measure or evaluate voltage drops to ensure that various components receive sufficient power across a range of operating conditions of the memory die, to predict voltages elsewhere in the pad or memory die, or for other purposes.

[0019] Therefore, it may be desirable to develop a simulation model of the die that, for example, accurately simulates the electrical response of the die a...

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PUM

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Abstract

Systems and apparatuses are provided for on-die memory power analytics and management are described. In some examples, the memory analytics and management may include a frequency-dependent analysis orsimulation model of a memory die to determine an operating characteristic of the die. A set of ports of the memory die may be selected and one or more alternating current (AC) excitation signals maybe applied to the ports to determine an impedance associated with the ports. The impedance may be used to determine one or more parameters (e.g., scattering, impedance) to analyze a die and for subsequently managing power distribution on the die. Analytics on a subset of ports on a die may be used to simulate the electrical response of the entire memory die and thus manage power delivery for the die.

Description

[0001] cross reference [0002] This patent application claims the benefits of U.S. Provisional Patent Application No. 62 / 804,329, entitled "ON-DIE MEMORY POWER ANALYTICS AND MANAGEMENT," filed February 12, 2019 by Badrieh et al. Priority, said U.S. Provisional Patent Application is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. technical field [0003] The technical field relates to on-die memory power analysis and management. Background technique [0004] The following relates generally to simulation of circuits, and more specifically to memory simulation tools for simulating the electrical response of a memory die. [0005] Memory devices are widely used to store information in various electronic devices such as computers, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented as a logic "...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/54G06F30/20
CPCG11C29/54G06F30/367G06F2119/06G11C29/50008G11C29/021G11C5/14G06F30/373Y02E60/00Y04S40/20G06F2115/12
Inventor F·巴德瑞尔T·H·金斯利B·崔
Owner MICRON TECH INC
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