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A kind of multi-layer stacked 3d-sip chip test method

A chip testing, multi-layer stacking technology, applied in electronic circuit testing, electrical measuring, measuring devices, etc., can solve the problem of increased difficulty in the testing stage, and achieve the effect of eliminating the need for a large number of pins and flexible application

Active Publication Date: 2022-03-29
WUXI ZHONGWEI TENGXIN ELECTRONICS
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  • Abstract
  • Description
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AI Technical Summary

Problems solved by technology

However, this also makes the testing phase more difficult
[0003] During the wafer stacking process, with the increase in the number of stacked wafers and the introduction of new defects in the manufacturing process, new testing challenges are brought

Method used

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  • A kind of multi-layer stacked 3d-sip chip test method
  • A kind of multi-layer stacked 3d-sip chip test method
  • A kind of multi-layer stacked 3d-sip chip test method

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Embodiment Construction

[0025] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0026] As an aspect of the present invention, a kind of 3D-SIP chip testing method of multi-layer stacking is provided, wherein, as figure 1 Shown, described 3D-SIP chip test method comprises:

[0027] S110. Acquiring a custom fault code table;

[0028] S120, load the test program to the chip test device;

[0029] S130. Perform a functional test on the multilayer integrated circuit chip according to the fault code custom table and in combination with the test program;

[0030] Wherein, the chip testing device is used for executing a test program and for installing the multi-layer integrated circuit chip.

[0031] The multi-layer stacked 3D-SIP chip testing m...

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Abstract

The invention relates to the technical field of integrated circuit testing, and specifically discloses a multi-layer stacked 3D-SIP chip testing method, wherein the 3D-SIP chip testing method includes: obtaining a fault code custom table; loading a test program to the chip test The device; according to the fault code self-definition table and combined with the test program, performs a functional test on the multi-layer integrated circuit chip; wherein, the chip testing device is used for executing the test program and for installing the multi-layer integrated circuit chip. The multi-layer stacked 3D-SIP chip testing method provided by the present invention realizes automatic functional testing of multi-layer integrated circuit chips, and saves the trouble of a large number of pins and complicated development programs, and can also be tested multiple times and applied flexibly , to achieve 100% functional testing.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a multilayer stacked 3D-SIP chip testing method. Background technique [0002] Wafer-level chips are heterogeneously integrated with a large number of cores, resulting in increased test complexity and cost. When designing 3D-SiP chips, some circuits may be divided into different wafer layers to minimize the interconnection length, which greatly improves the performance of 3D-SiP. However, this also makes the testing phase more difficult. [0003] During the wafer stacking process, with the increase in the number of stacked wafers and the introduction of new defects in the manufacturing process, new testing challenges are brought. Therefore, how to provide a test method suitable for multi-chip stacking has become a technical problem to be solved urgently by those skilled in the art. Contents of the invention [0004] The present invention aims to solve at l...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2851
Inventor 张凯虹徐德生奚留华武乾文
Owner WUXI ZHONGWEI TENGXIN ELECTRONICS
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