Packaging structure for rewiring after double-sided bump chip packaging and manufacturing method thereof

Abstract

The invention relates to a double-sided BUMP chip encapsulation rewiring package structure and a manufacturing method thereof, which includes a substrate (1) and a chip (2), and is characterized in that a plurality of through holes ( 3), and bumps (4) are provided on the front and back of the chip (2), the chip (2) is welded to the front of the substrate (1) through the bumps (4) on the front, and the chip (2) ) and the bumps (4) on the front and back of the chip (2) are encapsulated with a molding compound (5), the front of the molding compound (5) is flush with the top of the bumps (4) on the back of the chip (2), A metal circuit layer (6) is arranged on the front side of the molding compound (5), and the metal circuit layer (6) is connected to the bump (4) on the back side of the chip (2). The invention improves the flexibility of the top-layer chip loading form, reduces the height of the product, and shortens the path of signal transmission, thereby improving the quality of the signal.

Description

technical field [0001] The invention relates to a double-sided BUMP (bump) chip encapsulation and rewiring encapsulation structure and a manufacturing method thereof. It belongs to the technical field of electronic packaging. Background technique [0002] At present, there are three main stacking methods for products stacked in electronic packaging: [0003] The first is the ordinary stacking product, its structure is to stack chips directly on the chip, then wire bonding, and then encapsulation such as Figure 10 ; [0004] The second is the product of direct TSV stacking. Its structure is to use FC technology to stack chips on the chip after TSV, such as Figure 11 ; [0005] The third is to use POP technology to stack packages such as Figure 12 . [0006] There are following deficiencies in the above-mentioned mode of stacking products: [0007] The first is a common stacked product. This structure has restrictions on the top chip, not only the size of the chip, bu...

AI Technical Summary

Problems solved by technology

[0007] The first is a common stacked product. This structure has restrictions on the top chip, not only the size of the chip, but also the use of bonding wires to interconnect the chips;

[0008] The second is the product of direct TSV stacking. In this method, the flip position of the top chip cannot exceed the size of the bottom chip;

[0009] The third is to use POP technology to stack packages such as Figure 12 , the overall size of the package will be relatively thick due to the top-level packaged substrate in this way of stacking

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