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Fault diagnosis and recovery method of single-channel adc in multi-adc data acquisition system

A data acquisition system, fault diagnosis technology, applied in the direction of analog/digital conversion calibration/testing, etc.

Active Publication Date: 2016-11-16
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is currently no effective method to resynchronize the ADC after fault recovery with other ADCs without affecting the data acquisition of the normal channel ADC.

Method used

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  • Fault diagnosis and recovery method of single-channel adc in multi-adc data acquisition system
  • Fault diagnosis and recovery method of single-channel adc in multi-adc data acquisition system
  • Fault diagnosis and recovery method of single-channel adc in multi-adc data acquisition system

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Experimental program
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Embodiment Construction

[0012] The multi-channel synchronous data acquisition system is composed of a field programmable gate array FPGA and multiple ADCs, and each channel ADC is of the same model; the FPGA is connected with each channel ADC as a main controller to control synchronous conversion and acquisition of each channel ADC.

[0013] The ADC has a conversion timing control pin. When the pin receives an effective trigger pulse, the ADC will end the current analog-to-digital conversion state and start a new round of conversion; after each conversion of the ADC, a conversion will be generated. Completion of the flag signal; the ADC normally works in the continuous conversion mode, and the conversion completes the flag signal with a preset f DATA appear frequently.

[0014] Described FPGA respectively to the data update rate f of ADC of each channel DATA is monitored, if the FPGA logic measures f DATA If the value is inconsistent with the set value, it is considered to be a fault, otherwise it ...

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Abstract

The invention discloses a one-channel ADC (Analog to Digital Converter) fault diagnosis and recovery method in a multi-ADC data acquisition system. The method comprises the following steps: an FPGA (Field Programmable Gate Array) automatically diagnoses a failed ADC in a channel, and respectively monitors a data update rate of an fDATA in each channel; if an fDATA value monitored by an FPGA logic is not consistent with a set value, then a fault is detected, and otherwise a normal state is detected; after the FPGA diagnoses the failed ADC, the failed ADC is reset, and parameters of the failed ADC are reconfigured, wherein the reconfigured parameters completely refer to the ADC in a normal channel; and the FPGA, at a proper time point, sends an analog-to-digital conversion moment readjustment instruction to the failed ADC which is reset and reconfigured, and then data output synchronization can be achieved for the failed ADC and other ADCs in the normal channel. According to the invention, the characteristics of rapid diagnosis, high reliability, and the like are realized.

Description

technical field [0001] The invention belongs to the technical field of data acquisition, and in particular relates to a multi-channel parallel and synchronous data acquisition method. Background technique [0002] At present, in the field of inertial measurement, the accelerometer is used to measure the acceleration signal in the three-dimensional space of the moving body, and the navigation information is obtained by integrating the acceleration with respect to time. Acceleration can be integrated with time to obtain velocity, and velocity can be integrated once to obtain position information. Before time integration, it must be ensured that the acceleration data in the three directions are at the same moment, that is, time synchronization. Without synchronization, the navigation information derived from the integral is not reliable. In occasions where time synchronization is required for multi-channel synchronous data, the data acquisition system must be able to acquire ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10
Inventor 叶凌云宋开臣罗云黄添添朱智娟
Owner ZHEJIANG UNIV
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