Restrictive value delivery method and device applied to thread-level speculative parallelism

A value transfer and restrictive technology, applied in the field of computer microprocessor structure design, can solve problems such as large hardware cost, addition, complex bus structure of state transition diagram, etc., to solve the problem of false sharing, expand the scope of application, and reduce performance extremes poor effect

Active Publication Date: 2012-09-19
UNIV OF SCI & TECH OF CHINA
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Problems solved by technology

If you want to completely transplant this idea into the general directory structure, the state transition diagram will become more complicated than the bus structure, which is basically impossible to achieve in the real system
Finally, DATM adds a relatively large hardware cost to the general transaction storage system, which is also unwilling to accept by processor manufacturers.

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  • Restrictive value delivery method and device applied to thread-level speculative parallelism
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  • Restrictive value delivery method and device applied to thread-level speculative parallelism

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Embodiment Construction

[0032] The following will show the changes of the values ​​of the two sets of added registers through a program fragment with false sharing of data to illustrate the specific working process of the restricted value transfer technology in LogSPoTM. Attached Figure 5 (a) Two transactions are given, and they execute their respective codes. We assume that the priority of transaction 1 is higher than transaction 2, and each cache line has 4 bytes, that is to say, addresses 0 to 3 in the address space belong to the same cache line. In this way, transaction 1 and transaction 2 may trigger a conflict during conflict detection, although in fact they have no data dependency.

[0033] Attached Figure 5 (b) Gives the execution change process of the transaction. The data sending register set on the left is from the processor core where transaction 1 is located, and the data receiving register on the right is from the processor core running transaction 2. The steps are as follows:

[0034...

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Abstract

The invention provides a restrictive value delivery method and device applied to thread-level speculative parallelism, and when a conflict happens, the total execution time of a system can be reduced in a method of value delivery, i.e. a conflict thread can receive needed data only when a specific condition is met, and otherwise execution is conducted only according to the mode of the original system. The method disclosed by the invention is a lightweight class value delivery method, and compared with a complete value delivery and value prediction method, the method has the advantage of low hardware and protocol complexity, but under an ordinary condition, the performance is inferior to that of complete value delivery and value prediction. Through experimental data analysis, compared with a value prediction model, a restrictive value delivery model does not have large performance loss. The device is realized and verified on a LogSPoTM model, and is also suitable for other thread-level systems.

Description

Technical field [0001] The invention belongs to the field of computer microprocessor structure design, and particularly relates to a lightweight value transfer method and device that can effectively improve the performance of a multithreaded system. Background technique [0002] Speculative multi-threading technology and transaction storage technology [0003] With the advent of the era of multi-core chips (Chip Multi-Processor, CMP), how to thread serial programs that are traditionally difficult to parallelize to speed up the execution of a single program, while also providing more for more and more computing cores on the chip The computing tasks that can be executed in parallel to improve the utilization of on-chip resources have become a hot research issue of common concern in academia and industry. [0004] In order to develop more thread-level parallelism available on multi-core chips and solve the complexity and performance constraints brought by parallel program correctness m...

Claims

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Application Information

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IPC IPC(8): G06F9/46
Inventor 安虹邓博斌李颀李功明毛梦捷
Owner UNIV OF SCI & TECH OF CHINA
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