Method and control circuit for controlling physical layer chip

Abstract

The invention provides a method for controlling a physical layer (PHY) chip and a control circuit. The control circuit comprises a timing clock module, a first register module, a first state locking and storing module, a state rotation module and a management data input / output (MDIO) controller, wherein the state rotation module is used for reading the first register module according to a clock signal provided by the timing clock module and change information provided by the first state locking and storing module and providing first address information and control data information for the MDIO controller according to a reading result; and the MDIO controller is used for writing the control data information into a register of a pin of the PHY chip corresponding to the first address information so that the pin state of the PHY chip can be controlled automatically. After the technical scheme disclosed by the invention is adopted, the same MDIO controller can be used for managing multiplePHY chips so that the load of a central processing unit (CPU) is reduced.

Description

technical field [0001] The invention relates to communication technology, in particular to a method and a control circuit for controlling a physical layer chip. Background technique [0002] Existing large-scale network equipment usually adopts the General Purpose Input / Output (General Purpose Input / Output; referred to as: MDIO) bus to the physical layer (Physical Layer; : GPIO) pins to control some peripheral devices (such as light-emitting diodes) of the PHY chip. The MDIO bus is defined by the IEEE through several clauses of the Ethernet standard IEEE 802.3. The MDIO bus connects the management device (such as a microprocessor) with the PHY chip, so that the management device controls the PHY chip and collects status information from the PHY chip. [0003] There are two existing solutions for controlling the GPIO pins of the PHY chip based on the MDIO bus, namely a solution based on a Media Access Control (Media Access Control; MAC for short) chip and a solution based o...

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Problems solved by technology

[0004] In the process of realizing the present invention, the inventor found that the prior art has at least the following deficiencies: the solution based on the MAC chip is usually limited by the MAC chip, and it is impossible to use one MDIO controller to control multiple PHY chips at the same time

Although the solution based on FPGA can use one MDIO controller to control multiple PHY chips at the same time, the control process of each PHY chip requires the CPU to set the corresponding registers and control the access timing. Therefore, when multiple PHY chips are frequently controlled When the CPU is required to work non-stop, it will increase the burden on the CPU

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