Successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range

Abstract

The invention provides a successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range, comprising a simulation input signal, a successive approximation register integrator and a comparator, wherein the simulation input signal has simulation input voltage Vin, wherein the input signal of the successive approximation register integrator are three reference voltages comprising Vrp, Vrn and Vcm, and the output voltage Vda at an output end of the successive approximation register integrator is driven according to a binary search algorithm; the positiveinput end of the comparator is connected with the simulation input signal and the negative input end of the comparator is connected with the output voltage Vda of the integrator, the output end of the comparator gradually outputs N-bit digital signals. The requirement of the actual application can be effectively satisfied by the SARADC (successive approximation register analog-to-digital conversion) circuit within the minimal dynamic range by regulating the input reference voltage of the successive approximation register integrator; thus, the dynamic range of the SARADC circuit is not wasted;and besides, the cost of the actual circuit is saved.

Description

technical field [0001] The present invention relates to an analog-to-digital conversion circuit (Analog-to-Digital Converter, ADC), in particular to a method for effectively realizing the successive progressive conversion with the minimum dynamic range by adjusting the input reference voltage of the progressive progressive integrator. A near analog-to-digital conversion circuit (SAR ADC). Background technique [0002] Successive Approximation Register Analog-to-Digital Converter (SAR ADC) was born in Bell Laboratories in the 1940s in the United States. SAR ADC is still one of the main architectures of popular ADCs today. [0003] Although there are many ways to implement a SAR ADC, the basic structure is very simple. The analog input voltage Vin is maintained by the sample / hold circuit. Such as figure 1 As shown, the circuit schematic diagram of realizing SAR ADC for capacitive DAC. A capacitive DAC consists of N capacitors C arranged in binary weights 1 、C 2 、C 3 ,.....

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Problems solved by technology

[0013] The present invention proposes a successive asymptotic analog-to-digital conversion circuit (SAR ADC) that effectively realizes the minimum dynamic range by adjusting the input reference voltage of the successive asymptotic integrator, and solves the problem of wasted dynamic range in the existing SAR ADC. technical issues

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