Fault testing method for interconnection resource of programmable logic device

Abstract

The invention belongs to the technical field of an electron, particularly relates to an automated fault traversal testing method for an interconnection resource of a programmable logic device. The invention provides a method for automatically generating a test configuration set, which is irrelevant to the application; the weights of all sides are set according to the trend of a net by establishing a wiring resource map; and the configuration set is generated automatically by utilizing an improved Kruskal algorithm. For different interconnection structures of FPGA, the method achieves 100% coverage rate for the open circuit and short circuit fault in the interconnection resource, and has a few numbers of testing configurations, fast running speed and no dependency on a specified hardware structure.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to an automatic fault traversal test method for interconnection resources of general-purpose programmable logic devices. Background technique [0002] The general-purpose programmable logic device needs to ensure that the programmable logic device (Field Programmable Gate Array FPGA) chip can correctly realize the required circuit function for any user configuration. Usually, due to various user configurations, and with the increase of the FPGA chip scale, the time to configure the FPGA varies from milliseconds to seconds, so it is impossible to download all possible user configurations to the FPGA chip for troubleshooting Walk through the tests. In order to complete the fault traversal test of the FPGA chip, a special configuration set that has nothing to do with the application (Application Independent) must be downloaded to the FPGA chip to detect various faults ...

AI Technical Summary

Problems solved by technology

However, for the short-circuit fault of the interconnection segment, using the particularity of the hardware structure of the Virtex chip, all unused interconnection resources can be driven to "0" or "1", which has limitations in the hardware structure. In addition, for each The computational complexity required to map the interconnected resources in each direction is very high

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