Semiconductor device and method of manufacturing the same

A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as difficulty in realization, and achieve the effect of realizing terminal area, maintaining withstand voltage, and high withstand voltage

Inactive Publication Date: 2011-09-28
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

On the other hand, in order to increase the shared voltage of each guard ring, it is necessary to increase the curvature of the diffusion layer to ease the electric field, but there is a problem that it is difficult to achieve when the area of ​​each guard ring is reduced.

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0071]

[0072] figure 1 It is a sectional view of the terminal region of the power device chip of the present invention, showing a PN junction structure. The structure of a diode is described here as an example of a device. The channel stop area and scribe lines are omitted for convenience.

[0073] On the surface of the low-concentration N-type drift layer 2 formed (epitaxially grown) on the high-concentration N-type substrate 1, the P base layer 3 as the active layer is diffused to form a P base layer 3 to surround the active unit of the P base layer 3 region (a diode is formed in this embodiment), a P well layer 4 is formed as a first well region. The P well layer 4 is the main junction portion of the guard ring structure, and is adjacent to the P base layer 3 and diffused into a ring shape. Further, in the P well layer 4 , along its ring shape, a trench region 5 (sinking region) is formed as a ring-shaped concave portion having a tapered shape whose side surfaces exp...

Embodiment approach 2

[0110]

[0111] In Embodiment 1, the diffusion depth of the P base layer 3 is shallower than the diffusion depth of the P well layer 4, but as Figure 9 As shown, both can be set to the same degree of diffusion depth. The other configurations are the same as those in Embodiment 1, and therefore detailed descriptions are omitted.

[0112]

[0113] By forming the P base layer 3 and the P well layer 4 in this way, the electric field is not concentrated on one radius of curvature portion 22 of the P well layer 4, and the breakdown caused by the avalanche breakdown of the radius of curvature portion 22 is less likely to occur. Improve pressure resistance.

[0114]

[0115] According to Embodiment 2 of the present invention, in the semiconductor device, the diffusion depth of the P base layer 3 as the active layer and the P well layer 4 as the first well region on the high-concentration N-type substrate 1 as the semiconductor substrate is Therefore, the electric field does n...

Embodiment approach 3

[0117]

[0118] In Embodiment Mode 1, the trench region 5 having a tapered shape was formed by dry etching, but as Figure 10~Figure 13 As shown in the process, it can also be formed by the LOCOS (Local Oxidation of Silicon, local oxidation of silicon) oxidation process.

[0119] The following shows the LOCOS oxidation flow. first as Figure 10 As shown, a low-concentration N-type drift layer 2 is formed on a high-concentration N-type substrate 1 , and a nitride film 23 is used to form a pattern for forming a P well layer 4 on the low-concentration N-type drift layer 2 . Nitride film 23 is formed in a region other than the region to be P well layer 4 .

[0120] Then as Figure 11 As shown, the LOCOS oxide film 25 is formed by LOCOS oxidation. Then as Figure 12 As shown, the nitride film 23 and the LOCOS oxide film 25 are removed, and a photoresist 26 is formed so as to open the pattern to be the P well layer 4 . At this time, in the portion where the LOCOS oxide film ...

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Abstract

A semiconductor device according to the present invention includes: a cell active region including a p-base layer being an active layer of a second conductivity type that is diffused above a high concentration n-type substrate (1) being a semiconductor substrate of a first conductivity type; and a p-well layer (4) being a first well region of the second conductivity type having a ring shape, which is adjacent to the p-base layer (3), is diffused above the high concentration n-type substrate so as to surround the cell active region, and serves as a main junction part of a guard ring structure, wherein in a region on a surface of the p-well layer other than both ends, a trench region (5) that is a ring-shaped recess having a tapered side surface is formed along the ring shape of the p-well layer (4), the side surface widening upward.

Description

technical field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a terminal structure of a power semiconductor element, and to improving withstand voltage performance by relaxing the curvature of a diffusion layer. Background technique [0002] As semiconductor devices, especially power semiconductor elements, power devices are used as non-contact switches to control power, and are used in inverter circuits of home appliances such as air conditioners, refrigerators, washing machines, etc., as energy-saving continues to develop, and high-speed railways, subways, etc. in motor control. Furthermore, in recent years, in consideration of the global environment, it has been used as a power device for inverter / converter control of a hybrid car that uses both electricity and an engine, and as a power device for solar and wind power generation. , and its fields of application continue to expand. [0003] An importan...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/02H01L21/02
CPCH01L29/0615H01L29/66136H01L29/402H01L29/861H01L29/06H01L29/739
Inventor 楢崎敦司
Owner MITSUBISHI ELECTRIC CORP
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