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Programmable logic device graph drawing method and device

A technology of programming logic and graphic rendering, applied in instruments, special data processing applications, electrical digital data processing, etc., can solve the problems of poor user experience satisfaction, unfavorable designer design, lack of overall sense, etc., and achieves low display level, Conducive to design and avoids the effect of overall feeling

Active Publication Date: 2016-06-01
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The main technical problem to be solved by the present invention is to provide a programmable logic device graphics drawing method and device to solve the problems of slow response, low efficiency and poor user experience satisfaction when all graphics are drawn in the existing FPGA graphics, and when sampling and drawing It will lead to a lack of overall sense, which is not conducive to the design of the designer

Method used

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  • Programmable logic device graph drawing method and device
  • Programmable logic device graph drawing method and device
  • Programmable logic device graph drawing method and device

Examples

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Embodiment 1

[0071] In this embodiment, according to the display level, the modification frequency, and the number of updated objects, the programmable logic device is designed in a priority hierarchy, and it is first divided into a basic element layer containing all basic elements and a circuit design layer containing all related elements; wherein The basic element layer has a low display level, low modification frequency, and a large number of update objects, so it is the underlying base layer; on the contrary, the circuit design layer has a high display level, high modification frequency, and a small number of update objects. on the outermost layer. Based on this layered idea, see figure 1 As shown, the programmable logic device graphics drawing method provided in this embodiment includes:

[0072] Step 101: Construct the basic element layer of the current area to be drawn in the programmable logic device;

[0073] The basic element layer constructed here includes all elements in the ...

Embodiment 2

[0101] See Figure 5 As shown, this embodiment provides a programmable logic device graphics drawing device, including:

[0102] The basic element layer building module is used to construct the basic element layer of the current area to be drawn of the programmable logic device, and the basic element layer includes all elements of the current area to be drawn of the programmable logic device and all connection lines between the elements;

[0103] The circuit design layer construction module is used to select the design elements of the current area to be drawn of the programmable logic device from the basic element layer to form the circuit design layer; the design elements include the current design circuit used in the current area to be drawn of the programmable logic device All target elements and the currently used target connection lines between each target element.

[0104] Specifically, see Figure 6 As shown, the basic element layer construction module in this embodim...

Embodiment 3

[0121] For a better understanding of the present invention, this embodiment takes the application of the solution provided by the present invention to EDA to realize the drawing of FPGA diagram as an example to further illustrate the present invention.

[0122] Targeted for FPGA. In the hierarchical model, each level is prioritized according to the three dimensions of display level, modification frequency, and the number of updated objects. If the display level is high, the modification frequency is high, and the number of updated objects is small, it will be drawn at the top of the hierarchical model, and vice versa. The bottom layer of the model is drawn. To operate the interface, you only need to delete, redraw and superimpose one or several layers as needed.

[0123] For the FPGA layered model, please refer to Figure 10 Shown: FGPA is abstracted into a 5-layer model, sorted according to the display priority of different objects and the refresh frequency that needs to be...

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Abstract

The invention discloses a programmable logic device graph drawing method and device. When graph drawing is conducted on programmable logic devices of FPGA and the like, a basic element layer containing all basic elements is built, and then related target elements and currently used target connection circuits are selected according to the current design, and a designed circuit can be obtained. Therefore, when different designed circuits are drawn, drawing can be achieved by selecting the target elements and target connection circuits corresponding to the designed circuits on the basis of the basic element layer, complete redrawing is not needed, the drawing efficiency can be improved, the stuck screen and splash screen phenomena are avoided, and the satisfaction degree of user experience is promoted; meanwhile, all the elements on the basic element layer can be displayed, lack of sense of wholeness is avoided, and design of a designer is better facilitated.

Description

technical field [0001] The invention relates to the field of programmable logic devices, in particular to a method and device for drawing graphics of a programmable logic device. Background technique [0002] Field Programmable Logic Array (Field Programmable Gate Arrays or FPGA) is a pre-made silicon device, a typical programmable logic device, which can realize almost all types of digital circuits or digital systems through programming. Realized by a large number of logic blocks, memory, DSP (DigitalSignalProcessor, digital signal processor). Since FPGA is a programmable device, its circuit design software (Electronic Design Automation, EDA) is particularly important. Among them, layout planning, mapping, placement and routing are the main processes of chip logic. [0003] As a chip design software, EDA must abstract the logic structure, wiring method and timing of FPGA logic gates according to the model, making the design more intuitive and easy to understand. A large n...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 刘仁杰张敏
Owner SHENZHEN PANGO MICROSYST CO LTD
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