Three-dimensional integration method of CMOS image sensor

Abstract

The invention belongs to the technical field of semiconductor technology, in particular to a three-dimensional integration method of a CMOS image sensor. The method includes: providing a CMOS image sensor chip fabricated on a fully depleted SOI wafer; forming a first metal interconnection wiring layer and a passivation layer; forming an embedded electrode on the first metal interconnection; cutting the CMOS image sensor chip and performing surface plasma activation processing; and bonding the embedded electrodes of the two CMOS image sensor chips to each other. According to the three-dimensional COMS image sensor, an embedded electrode is used for directly bonding a silicon layer on an insulator to obtain a high-density stacked three-dimensional COMS image sensor without required extra space. The three-dimensional integration method of a CMOS image sensor is suitable for high-density integration.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a three-dimensional integration method of a CMOS image sensor. Background technique [0002] CMOS image sensor three-dimensional integration technology mainly includes through-silicon via (TSV) technology, sequential integration technology and silicon-on-insulator (SOI)-based assembly technology. The interconnection size of TSV technology is generally greater than 5 μm, which is not suitable for high-density integrated circuits with a through hole size of 5 μm or less, and it is difficult to integrate stacked CMOS image sensors with pixel interconnections. Although sequential integration technology, SOI-based assembly technology has the potential to achieve high-density storage, TSVs need to be formed in the outer region of the field-effect transistor, thereby limiting circuit density. Contents of the invention [0003] In order to solve the above problems, ...

AI Technical Summary

Problems solved by technology

The interconnection size of TSV technology is generally greater than 5 μm, which is not suitable for high-density integrated circuits with a through hole size of 5 μm or less, and it is difficult to integrate stacked CMOS image sensors with pixel interconnections

Although sequential integration technology, SOI-based assembly technology has the potential to achieve high-density storage, TSVs need to be formed in the outer area of ​​​​the field effect transistor, thereby limiting circuit density

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