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ESD (Electronic Static Discharge) protection device

A technology of ESD protection and binding posts, which is applied in the direction of emergency protection circuit devices, circuit devices, emergency protection circuit devices for limiting overcurrent/overvoltage, etc., which can solve problems such as inability to protect internal circuits and high trigger voltage, and achieve protection Internal circuit, the effect of eliminating excessive voltage

Active Publication Date: 2012-05-23
STATE GRID CORP OF CHINA +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The problem solved by the present invention is to provide an ESD protection device to solve the problem that the trigger voltage of the existing ESD protection device is too high and cannot effectively protect the internal circuit

Method used

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  • ESD (Electronic Static Discharge) protection device
  • ESD (Electronic Static Discharge) protection device
  • ESD (Electronic Static Discharge) protection device

Examples

Experimental program
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Effect test

no. 1 example

[0022] The ESD protection device of this embodiment is such as figure 2 As shown, the device is located on a P substrate, including a thyristor 10 and a depletion NMOS transistor 20 .

[0023] The thyristor 10 includes a parasitic PNP transistor T1 and a parasitic NPN transistor T2; the emitter of the parasitic PNP transistor T1 is connected to the anode terminal 30, and its base is connected to the anode terminal 30 through the parasitic resistance Rn1 of the first N well; The emitter of the parasitic NPN transistor T2 is connected to the cathode terminal 40, and its base is connected to the cathode terminal 40 through the P well parasitic resistance Rp; the thyristor 10 also includes a P well located in the P well. + well contact, the P + The well contact is connected to the base of the parasitic NPN transistor T2. like figure 2 Shown, preferably, the P + well contact located on the first N-well of the thyristor 10 P + and P-well N + between.

[0024] The gate of th...

no. 2 example

[0035] The ESD protection device of this embodiment is as follows Figure 4 As shown, the device is located on an N substrate and includes a thyristor 50 and a depletion-mode PMOS transistor 60 .

[0036] The thyristor 50 includes a parasitic PNP transistor T3 and a parasitic NPN transistor T4; the emitter of the parasitic PNP transistor T3 is connected to the anode terminal 30, and its base is connected to the anode terminal 30 through the N-well parasitic resistance Rn; the parasitic The emitter of the NPN transistor T4 is connected to the cathode terminal 40, and its base is connected to the cathode terminal 40 through the parasitic resistance Rp1 of the first P-well; the thyristor 50 further includes a P-well located in the first P-well + well contacts, the P + The well contact is connected to the base of the parasitic NPN transistor T4.

[0037] The gate of the PMOS transistor 60 is positively biased; the drain of the PMOS transistor 60 is connected to the anode termina...

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Abstract

The invention discloses an ESD (Electronic Static Discharge) protection device which comprises a thyristor. The thyristor comprises a parasitic PNP (Positive Negative Positive) tube and a parasitic NPN (Negative Positive Negative) tube, wherein the emitting electrode of the parasitic PNP tube is connected with an anode wiring terminal, and the base electrode of the parasitic PNP tube is also connected with the anode wiring terminal through a trap N parasitic resistor; and the emitting electrode of the parasitic NPN tube is connected with a cathode wiring terminal, and the base electrode of the parasitic NPN tube is also connected to the cathode wiring terminal through a trap P parasitic resistor. The thyristor also comprises a trap P+ contact on the trap P and a depletion type MOS (MetalOxide Semiconductor) tube, wherein the trap P+ contact is connected with the base electrode of the parasitic NPN tube; bias voltage is applied to the grid electrode of the MOS tube, and the drain electrode of the MOS tube is connected to the anode wiring terminal through a trap resistor connected with the drain electrode; and the source electrode of the MOS tube is connected with the trap P+ contact. The ESD protection device has low trigger voltage and can quickly discharge ESD current, eliminate ESD overhigh voltage and effectively protect an internal circuit.

Description

technical field [0001] The invention relates to the field of protection circuit design of semiconductor integrated circuits, in particular to an ESD protection device. Background technique [0002] During the manufacture, packaging and use of integrated circuit chips, ESD (Electro Static Discharge, electrostatic discharge) phenomenon will occur. ESD is manifested as an instantaneous high-voltage pulse, and the large amount of charge released in this instant is very likely to destroy the functional devices inside the integrated circuit. Therefore, a protection device is usually provided between the internal circuit and the external signal source or power supply. [0003] At present, the commonly used protection devices use thyristors. A protection device consisting of a thyristor such as figure 1 shown, where the left P + , N well, right P well, N + constitutes a thyristor, the N on the left + and P + common connection to the anode terminal, N on the right + and P + ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L23/60H02H9/00
CPCH01L2924/0002
Inventor 单毅
Owner STATE GRID CORP OF CHINA
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